In recent years, for further improvement in the performance of semiconductor devices such as speeding up and an increase in the capacity, research and development is in progress to improve the performance by a three-dimensional (3D) lamination having at least two semiconductor substrates laminated, in addition to refinement of transistors and wiring.
Specifically, such a process is proposed (non-Patent Documents 1 and 2) that a thin film of an interlayer filler composition is formed by an underfilling process of pouring a filler from the side of semiconductor substrates after bonding of the substrates or by application to a wafer, and then B-stage formation is carried out, then semiconductor substrates are cut out by dicing (wafer cutting), temporary bonding by pressure heating is repeatedly carried out by using the semiconductor substrates, and finally main bonding (solder bonding) is carried out under pressure heating conditions to form a three-dimensional integrated circuit laminate.
For practical use of such a three-dimensional integrated circuit device, various problems have been pointed out. One of them is a problem of dissipation of heat generated from a device such as a transistor or wiring. This problem results from a commonly very low thermal conductivity of an interlayer filler composition to be used for lamination of semiconductor substrates as compared with metals and ceramics, and there are concerns about a decrease in the performance such as malfunction of a semiconductor device due to accumulation of heat in a laminate of the semiconductor substrates.
As a further problem, the coefficient of linear thermal expansion required for the interlayer filler composition varies depending upon the difference in the structure of a laminate of the semiconductor substrates. In a three-dimensional integrated circuit laminate comprising a semiconductor substrate laminate having semiconductor substrates bonded and laminated, the interlayer filler layer formed between the semiconductor substrates preferably has low linear thermal expansion property.
As another problem, there is a problem of the dielectric constant of the interlayer filler composition to be used for lamination of a semiconductor device. In recent years, the operating frequency of a semiconductor device increases year by year, and the conduction velocity exceeding the GHz level is required for signal transmission between semiconductor substrates not only inside a semiconductor substrate. On that occasion, if the dielectric constant of an interlayer filler composition to be used for lamination of a semiconductor device is high, signal transmission delays in wiring between substrates will occur, thus leading to a decrease in the operating speed of the entire device.
On the other hand, in a three-dimensional integrated circuit laminate having the semiconductor substrate laminate further bonded to an organic substrate, to an interlayer filler layer formed between the semiconductor substrate laminate and the organic substrate, a potential stress is applied due to a difference in the coefficient of linear thermal expansion by heat between the semiconductor substrates and the organic substrate, and accordingly if the interlayer filler layer does not have an appropriate coefficient of linear thermal expansion, destruction of the semiconductor device layer, breakage of the electric signal connection terminal, or the like may occur in some cases.
As one means to solve the problems, an increase in thermal conductivity of the interlayer filler composition applied to between the substrates of a three-dimensional integrated circuit laminate may be mentioned. For example, a highly thermally conductive epoxy resin is used as a resin itself constituting the interlayer filler composition, or such a resin is combined with a highly thermally conductive inorganic filler, to try to make the interlayer filler composition be highly thermally conductive. For example, a resin composition having high thermal conductivity by an epoxy resin having mesogen (a structure which is likely to be self-aligned) and a curing agent has been reported (Patent Document 1).
Further, in order to control the coefficient of linear thermal expansion of the interlayer filler while suppressing an increase in the dielectric constant, it has been disclosed to blend silica particles as an inorganic filler in a resin (Patent Document 2).
Further, it has been disclosed to blend boron nitride having high thermal conductivity, not a conventional silica filler, as an inorganic filler in a resin (Patent Document 3).